Vertical light emitting devices with nickel silicide bonding and methods of manufacturing

ABSTRACT

Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series. The bonding material contains nickel (Ni). The method also includes placing the light emitting structure onto a silicon substrate with the bonding material in contact with the silicon substrate and annealing the light emitting structure and the silicon substrate. As a result, a nickel silicide (NiSi) material is formed at an interface between the silicon substrate and the bonding material to mechanically couple the light emitting structure to the silicon substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 15/815,568 file Nov. 16, 2017, which is a continuation of U.S. application Ser. No. 15/254,483 filed Sep. 1, 2016, now U.S. Pat. No. 9,842,976, which is a continuation of U.S. application Ser. No. 14/456,730, filed Aug. 11, 2014, now U.S. Pat. No. 9,455,386, which is a divisional of U.S. application Ser. No. 13/053,932 filed Mar. 22, 2011, now U.S. Pat. No. 8,802,461, which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure is related generally to light emitting devices (e.g., light emitting diodes (“LEDs”)) with a nickel silicide (NiSi) bonding interface and associated methods of manufacturing.

BACKGROUND

During the manufacturing of LEDs with vertical contacts, the LEDs are typically first formed on a growth substrate and subsequently bonded to a carrier via copper-copper (Cu—Cu) or nickel-tin (Ni—Sn) bonding. FIGS. 1A-1C illustrate a process for manufacturing an LED with Ni—Sn bonding in accordance with the prior art. As shown in FIG. 1A, the process initially includes forming N-type gallium nitride (GaN) 14, GaN/indium gallium nitride (InGaN) multiple quantum wells (“MQWs”) 16, and P-type GaN 18 on a substrate material 12 with a buffer material 13. Subsequently, a first metal stack 19 is formed on the P-type GaN 18 via sputtering, electrolysis, and/or other suitable techniques. The first metal stack 19 includes a barrier material 20 (e.g., tungsten/titanium (W/Ti)), a copper (Cu) seed material 22, nickel (Ni) 24, and tin (Sn) 26.

As shown in FIG. 1B, a similar second metal stack 19′ is formed on a carrier 32. The second metal stack 19′ includes a barrier material 20′, a copper (Cu) seed material 22′, nickel (Ni) 24′, and tin (Sn) 26′. The multiple materials of the first and second metal stacks 19 and 19′ are selected based on a target stress level on the substrate material 12. As shown in FIG. 1C, the substrate material 12 with the first metal stack 19 is then stacked on the carrier 32 such that the first and second metal stacks 19 and 19′ face each other. The first and second metal stacks 19 and 19′ are then bonded to each other using an annealing process to form an assembly 10. The substrate material 12 (shown in phantom lines) is then removed from the assembly 10 before the assembly 10 is diced into individual LED dies.

The bonded substrate material 12 and the carrier 32 formed according to the process discussed above tend to bow and/or otherwise flex with temperature fluctuations. Such flexure can crack and/or otherwise damage the N-type GaN 14, the GaN/InGaN MQWs 16, and/or the P-type GaN 18. Also, it has been observed that various materials in the first and/or second metal stacks 19 and 19′ tend to peel off from the assembly 10 during dicing. It is believed that delamination between two adjacent materials in the first and second metal stacks 19 and 19′ contribute to such delamination. In addition, the foregoing assembling process is time consuming and costly because a large number of metals are deposited in series. Accordingly, several improvements to the bonding techniques used to efficiently manufacture LED dies may be desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C illustrate a process for manufacturing an LED with Ni—Sn bonding in accordance with the prior art.

FIGS. 2A-2H illustrate a process for manufacturing an LED with Ni—Si bonding in accordance with selected embodiments of the technology.

FIGS. 3A-3F illustrate a process for manufacturing an LED with Ni—Si bonding in accordance with additional embodiments of the technology.

DETAILED DESCRIPTION

Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described below. As used hereinafter, the term “light emitting device” generally refers to LEDs, laser diodes, and/or other suitable solid state sources of illumination other than electrical filaments, a plasma, or a gas. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to FIGS. 2A-3F.

FIGS. 2A-2H illustrate a process for manufacturing a light emitting device 100 with Ni—Si bonding in accordance with selected embodiments of the technology. In the following description, common acts and structures are identified by the same reference numbers. Even though only particular processing operations and associated structures are illustrated in FIGS. 2A-2H, in certain embodiments, the process can also include forming a lens, a mirror, suitable support structures, conductive interconnects, and/or other mechanical/electrical components (not shown) associated with a packaged light emitting device.

As shown in FIG. 2A, an initial stage of the process can include forming a first semiconductor material 104, an active region 106, and a second semiconductor material 108 (collectively referred to as a “light emitting structure 111” hereinafter) on a substrate material 102. In one embodiment, the substrate material 102 includes a silicon (Si) wafer with a Si(1,1,1) crystal orientation at a surface 102 a of the substrate material 102. In other embodiments, the substrate material 102 can also include aluminum gallium nitride (AlGaN), GaN, silicon carbide (SiC), sapphire (Al₂O₃), a combination of the foregoing materials, and/or other suitable substrate materials.

In the illustrated embodiment, the substrate material 102 optionally includes a first buffer material 103 a and a second buffer material 103 b (collectively referred to as buffer materials 103) on the surface 102 a. The optional buffer materials 103 can individually include aluminum nitride (AlN), GaN, zinc nitride (ZnN), and/or other suitable materials. In other embodiments, the substrate material 102 may include only one of the buffer materials 103. In further embodiments, the buffer materials 103 may be omitted, and the light emitting structure 111 may be formed directly on the surface 102 a of the substrate material 102. In yet further embodiments, other intermediate materials (e.g., zinc oxide (ZnO₂)) may be formed on the substrate material 102 in addition to or in lieu of the buffer materials 103.

In one embodiment, the first and second semiconductor materials 104 and 108 include an N-type GaN material and a P-type GaN material, respectively. In another embodiment, the first and second semiconductor materials 104 and 108 include a P-type GaN material and an N-type GaN material, respectively. In further embodiments, the first and second semiconductor materials 104 and 108 can individually include at least one of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), gallium(III) phosphide (GaP), zinc selenide (ZnSe), boron nitride (BN), AlGaN, and/or other suitable semiconductor materials.

The active region 106 can include a single quantum well (“SQW”), MQWs, and/or a bulk semiconductor material. As used hereinafter, a “bulk semiconductor material” generally refers to a single grain semiconductor material (e.g., InGaN) with a thickness greater than about 10 nanometers and up to about 500 nanometers. In certain embodiments, the active region 106 can include an InGaN SQW, InGaN/GaN MQWs, and/or an InGaN bulk material. In other embodiments, the active region 106 can include aluminum gallium indium phosphide (AIGalnP), aluminum gallium indium nitride (AlGaInN), and/or other suitable materials or configurations. In any of the foregoing embodiments, the first semiconductor material 104, the active region 106, the second semiconductor material 108, and the buffer materials 103 can be formed on the substrate material 102 via metal organic chemical vapor deposition (“MOCVD”), molecular beam epitaxy (“MBE”), liquid phase epitaxy (“LPE”), hydride vapor phase epitaxy (“HVPE”), and/or other suitable epitaxial growth techniques.

An optional stage of the process can include forming a conductive material 110 on substantially the entire surface area of the second semiconductor material 108. The conductive material 110 is at least partially transparent to the radiation generated by the light emitting structure 111. In certain embodiments, the conductive material 110 can include indium tin oxide (“ITO”), aluminum zinc oxide (“AZO”), fluorine-doped tin oxide (“FTO”), and/or other suitable transparent conductive oxide (“TCOs”). In other embodiments, the conductive material 110 can include other suitable conductive and transparent materials. Techniques for forming the conductive material 110 can include MOCVD, MBE, spray pyrolysis, pulsed laser deposition, sputtering, electroplating, and/or other suitable deposition techniques. In further embodiments, the conductive material 110 may be omitted.

FIG. 2B illustrates another stage of the process, in which a plurality of openings 112 are formed in the optional conductive material 110 and the light emitting structure 111, and a passivation material 114 is formed or deposited in the openings 112. The openings 112 individually contain passivation material 114. Two openings 112 are shown in FIG. 2B for illustration purposes, though any other desired numbers of openings 112 may be formed. In certain embodiments, the individual openings 112 can delineate individual light emitting dies 113. In other embodiments, the openings 112 can insulate and/or form other suitable structures between adjacent sections of the light emitting structure 111 in addition to or in lieu of delineating the individual light emitting dies 113.

In the illustrated embodiment, the openings 112 include sidewalls 115 extending through the conductive material 110, the first semiconductor material 104, the active region 106, the second semiconductor material 108, the buffer materials 103, and into a portion of the substrate material 102. In other embodiments, at least some of the openings 112 include sidewalls 115 extending through the conductive material 110 into a portion of the buffer materials 103 without extending into the substrate material 102. In further embodiments, the openings 112 can include sidewalls 115 extending through the conductive material 110 into a portion of the first semiconductor material 104 without extending into the buffer material 103. In any of the foregoing embodiments, the openings 112 can include sidewalls 115 extending through at least the active region 106 of the light emitting structure 111.

The passivation material 114 can include at least one of silicon oxide (SiO₂), silicon nitride (Si₃N₄), and/or other suitable insulative materials. In the illustrated embodiment, the passivation material 114 only partially fills the openings 112. Thus, the passivation material 114 includes a first end 114 a proximate the substrate material 102 and a second end 114 b recessed from the conductive material 110. As such, the second end 114 b is spaced apart from the conductive material 110 in this embodiment. In other embodiments, the passivation material 114 may completely fill the openings 112 such that the second end 114 b is generally planar with the conductive material 110. In further embodiments, the passivation material 114 may be a thinner structure that generally conforms to the contour of the substrate material 102 and the sidewalls 115 of the openings 112 without filling the openings 112. In any of the foregoing embodiments, the passivation material 114 covers at least the active region 106 of the light emitting structure 111.

FIG. 2C illustrates another stage of the process in which a barrier material 116, a mirror material 118, and a bonding material 120 (collectively referred to as a bonding stack 122) are formed on the optional conductive material 110 in series. The barrier material 116 can include nickel (Ni), tantalum (Ta), cobalt (Co), ruthenium (Ru), tantalum nitride (TaN), indium oxide (In₂O₃), tungsten nitride (WN₂), titanium nitride (TiN), and/or other suitable diffusion resistant materials. The mirror material 118 can include silver (Ag), aluminum (Al), and/or other suitable reflective materials. The bonding material 120 can include nickel (Ni) and/or a nickel alloy with a thickness between about 100 Angstroms and about 300 Angstroms or other suitable thickness values. Techniques for forming the barrier material 116, the mirror material 118, and the bonding material 120 can include sputtering, electroplating, and/or other suitable deposition techniques.

In the illustrated embodiment, the bonding stack 122 include a first bonding portion 122 a on the optional conductive material 110 and a second bonding portion 122 b in the individual openings 112. The end of the second bonding portion 122 b can abut the passivation material 114. In other embodiments, the first bonding portion 122 a may be formed directly on the second semiconductor material 108 when the conductive material 110 is omitted. In further embodiments in which the passivation material 114 generally conforms to the sidewalls 115 of the openings 112, the second bonding portion 122 b may extend into a cavity in the passivation material as deep as the first semiconductor material 104 and/or the buffer materials 103. In embodiments in which the passivation material 114 is planar to the surface of the light emitting structure 111, the second bonding material 112 b can also be generally planar.

FIG. 2D illustrates another stage of the process, in which the light emitting structure 111 is mounted on a carrier 132 with the bonding stack 122 in direct contact with a surface 132 a of the carrier 132. In one embodiment, the carrier 132 can include a silicon (Si) wafer with a Si(1,0,0) crystal orientation and with P-type doped (e.g., with boron (B)) polysilicon at the surface 132 a of the carrier 132. In other embodiments, the silicon wafer may have other doping characteristics or may be undoped. In further embodiments, the carrier 132 may include a ceramic and/or other suitable types of carrier materials. Even though the carrier 132 is shown as a single material in FIG. 2D, in further embodiments, the carrier 132 may also include a heat sink, electrodes, and/or other suitable structures and components.

An optional stage of the process can include polishing and/or cleaning the surface 132 a of the carrier 132 before to mounting the light emitting structure 111 thereon. In one embodiment, the carrier 132 may be polished using chemical mechanical polishing (“CMP”), electrochemical-mechanical polishing (“ECMP”), and/or other suitable polishing techniques. As a result, the surface 132 a can be at least partially planarized. In other embodiments, the surface 132 a of the carrier 132 may also be treated with a solution of hydrofluoric acid (HF), a base (e.g., potassium hydroxide (KOH)), an oxidizer (e.g., hydrogen peroxide (H₂O₂), and/or other suitable compositions. After the treatment, adsorbed particles may be removed from the surface 132 a. Surface oxides, nitrides, and/or other compounds of silicon may also be removed. As a result, the carrier 132 includes exposed silicon atoms on the surface 132 a that are in direct contact with the bonding material 120 of the bonding stack 122.

FIG. 2E illustrates a subsequent stage of the process in which the light emitting structure 111 and the carrier 132 are bonded together. In FIG. 2E, a portion of the interface between the bonding stack 122 and the carrier 132 is enlarged for clarity. In certain embodiments, bonding the light emitting structure 111 to the carrier 132 includes heating at least the bonding stack 122 and the carrier 132 to a bonding temperature via conduction, convection, radiation, a combination thereof or by other suitable means. The bonding temperature can be maintained for a period of time (referred to hereinafter as the “bonding period”) under a bonding pressure. The bonding temperature can be from about 300° C. to about 450° C. (e.g., 300° C., 350° C., 400° C., or 450° C.), and/or other suitable values. The bonding period can last from about 1 to about 30 minutes and/or other suitable values. The bonding pressure can be from about 50 mPa to about 100 mPa (e.g., 50 mPa, 55 mPa, 60 mPa) and/or other suitable values.

Without being bound by theory, it is believed that the heating of the bonding stack 122 and the carrier 132 causes at least a portion of the bonding material 120 containing nickel (Ni) to react with the P-type polysilicon (and/or other silicon materials) on the surface 132 a of the carrier 132. The reaction consumes a portion of the bonding material 120 and forms nickel silicide (NiSi) 136 at the interface between the carrier 132 and the bonding material 120 to mechanically bond the light emitting structure 111 and the carrier 132 together. The formed NiSi 136 may have a thickness between about 10 Angstroms and about 100 Angstroms.

In any of the foregoing embodiments, the process can include adjusting at least one of the bonding temperature, the bonding period, the bonding pressure, and/or other suitable operating conditions based on the desired thickness of the bonding material 120 remaining after the completion of the reaction. In one embodiment, the desired remaining thickness of the bonding material 120 is greater than about 30 Angstroms. In other embodiments, the desired remaining thickness of the bonding material 120 can be 40 Angstroms, 50 Angstroms, and/or other suitable thickness values.

In several embodiments, the remaining unconsumed portion of the bonding material 120 can form a diffusion barrier between the mirror material 118 and the carrier 132. As a result, the desired thickness of the remaining bonding material 120 can be determined based on empirical data and/or other suitable information so that the remaining bonding material 120 can prevent the mirror material 118 from migrating to the carrier 132. In further embodiments, the bonding material 120 may be completely consumed when the bonding stack 122 includes an additional diffusion barrier (not shown) between the mirror material 118 and the carrier 132.

FIG. 2F illustrates another stage of the process, in which the substrate material 102 and the buffer materials 103 are removed from the light emitting structure 111. Techniques for removing the substrate material 102 and the buffer materials 103 can include back grinding, dry etching, wet etching, and/or other suitable material removal techniques. In the illustrated embodiment, the material removal operation is stopped at the first semiconductor material 104. In other embodiments, a portion of the first semiconductor material 104 may also be removed from the light emitting structure 111.

FIG. 2G illustrates another stage of the process, in which first electrodes 138 are formed on the first semiconductor material 104. In one embodiment, forming the first electrodes 138 can include depositing an electrical conductor (e.g., aluminum (Al), titanium (Ti), and/or an aluminum/titanium (Al/Ti) alloy) on the first semiconductor material 104 via sputtering and/or other suitable techniques. Subsequently, the deposited electrical conductor can be patterned based on a desired electrode pattern. During the deposition and/or patterning operations, the process can also include controlling the temperatures of these operations to be below the stability temperature of the NiSi 136. In one embodiment, the target stability temperature is about 550° C. In other embodiments, the target stability temperature can be about 600° C., 650° C., 700° C., and/or other suitable temperature values.

FIG. 2H illustrates another stage of the process, in which the individual light emitting dies 113 are singulated along the openings 112. As a result, at least a section of the second bonding portions 122 b remain on sidewalls 115 of the individual light emitting dies 113. Techniques for singulating the individual light emitting dies 113 can include dicing, laser ablation, dry etching, and/or other suitable techniques. Subsequently, the process can also include cleaning, packaging, and/or other suitable post-processing operations (not shown).

Several embodiments of the process discussed above with reference to FIGS. 2A-2H can bond the light emitting structure 111 to the carrier 132 more efficiently than conventional techniques. As discussed with reference to FIGS. 1A-1C, the conventional Ni—Sn bonding technique requires at least four metal materials to be formed on each of the substrate material 12 (FIG. 1A) and the carrier 32 (FIG. 1B). In contrast, certain embodiments of the current technique include reacting a portion of the bonding material 120 with a silicon material on the carrier 132 and using the remaining portion of the bonding material 120 as a diffusion barrier. As a result, the number of deposition operations can be significantly reduced as compared to the conventional technique, thus reducing manufacturing complexity and costs.

Even though the process discussed above with reference to FIGS. 2A-2H includes forming the plurality of openings 112 prior to forming the bonding stack 122 on the light emitting structure 111, in other embodiments, the sequence of the process may be different and/or include other operations. For example, FIGS. 3A-3F illustrate another embodiment of the process, in which the bonding stack 122 is formed on the light emitting structure 111 without forming the openings 112.

As shown in FIG. 3A, an initial stage of the process can include forming the bonding stack 122 on the optional conductive material 110. Like reference numbers refer to common components in FIGS. 2A-3F. Unlike the embodiments shown in FIG. 2C, the bonding stack 122 in FIG. 3A is generally planar. As shown in FIG. 3B, the light emitting structure 111 is mounted on the carrier 132 with the bonding stack 122 in direct contact with a surface 132 a of the carrier 132. Subsequently, as shown in FIG. 3C, the light emitting structure 111 and the carrier 132 are bonded together with techniques generally similar to those discussed above with reference to FIG. 2E. As shown in FIG. 3D, the substrate material 102 and the optional buffer materials 103 have been removed from the light emitting structure 111. As shown in FIG. 3E, first electrodes 138 can then be formed on the exposed first semiconductor material 104. The light emitting structure 111 and the bonded carrier 132 can then be singulated into individual light emitting dies 113, as shown in FIG. 3F.

Several embodiments of the process discussed above with reference to FIGS. 3A-3F may have a higher bonding strength between the bonding material 120 and the carrier 132 than that discussed above with reference to FIGS. 2A-2H because the interface therebetween is generally continuous, as shown in FIGS. 3B and 3C. Also, several embodiments of the process discussed above further simplify the process discussed above with reference to FIGS. 2A-2H by eliminating the formation of the openings 112 and deposition of the passivation material 114 therein. As a result, the complexity and costs related to the process may be further reduced as compared to conventional techniques.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the disclosure is not limited except as by the appended claims. 

I/We claim:
 1. A light emitting device, comprising: a silicon substrate; a nickel silicide layer disposed over and in direct contact with the silicon substrate; a first diffusion barrier layer disposed over and in direct contact with the nickel silicide layer; a mirror layer disposed over and in direct contact with the diffusion barrier layer; a second diffusion barrier layer disposed over and in direct contact with the mirror layer; and a light emitting structure disposed over the second diffusion barrier layer.
 2. The light emitting device of claim 1, wherein the first diffusion barrier layer comprises an unconsumed portion of either a nickel layer or a nickel alloy layer from which the nickel silicide layer was at least partially formed.
 3. The light emitting device of claim 1, wherein the first diffusion barrier layer has a thickness between about 100 Angstroms and about 300 Angstroms.
 4. The light emitting device of claim 1, wherein the second diffusion barrier layer comprises nickel (Ni), tantalum (Ta), cobalt (Co), ruthenium (Ru), tantalum nitride (TaN), indium oxide (In₂O₃), tungsten nitride (WN₂), titanium nitride (TiN), or a combination thereof.
 5. The light emitting device of claim 1, wherein the mirror layer comprises silver (Ag), aluminum (Al), or a combination thereof.
 6. The light emitting device of claim 1, further comprising a conductive material layer between the light emitting structure and the second diffusion barrier layer.
 7. The light emitting device of claim 6, wherein the conductive material layer comprises indium tin oxide, aluminum zinc oxide, fluorine-doped tin oxide, or a combination thereof.
 8. The light emitting device of claim 1, wherein the light emitting structure includes a first semiconductor material, a second semiconductor material, and an active region disposed between the first semiconductor material and the second semiconductor material.
 9. The light emitting device of claim 8, wherein the first semiconductor material and the second semiconductor material each comprise one of an N-type gallium nitride (GaN) material, a P-type GaN material, gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), gallium(III) phosphide (GaP), zinc selenide (ZnSe), boron nitride (BN), aluminum gallium nitride (AlGaN), or a combination thereof.
 10. The light emitting device of claim 8, wherein the active region comprises a single quantum well (“SQW”), multiple quantum wells (“MQWs”), aluminum gallium indium phosphide (AlGaInP), aluminum gallium indium nitride (AlGaInN), or a combination thereof.
 11. The light emitting device of claim 8, wherein the active region comprises an InGaN SQW, InGaN/GaN MQWs, an InGaN bulk material, or a combination thereof.
 12. The light emitting device of claim 8, wherein the active region has a thickness between about 10 nanometers and about 500 nanometers.
 13. The light emitting device of claim 1, wherein second diffusion barrier layer includes a first bonding portion and a second bonding portion, wherein the first bonding portion is on a lower surface of the light emitting structure, and wherein the second bonding portion is on a sidewall of the light emitting structure.
 14. The light emitting device of claim 13, further comprising a passivation material on the sidewall of the light emitting structure, the passivation material abutting the second bonding portion.
 15. The light emitting device of claim 1, further comprising at least one electrode disposed over the light emitting structure.
 16. The light emitting device of claim 15, wherein the at least one electrode comprises aluminum (Al), titanium (Ti), or a combination thereof.
 17. A light emitting device, comprising: a silicon substrate; a nickel silicide layer disposed over and in direct contact with the silicon substrate; a first diffusion barrier layer disposed over and in direct contact with the nickel silicide layer; a mirror layer disposed over and in direct contact with the diffusion barrier layer; a second diffusion barrier layer disposed over and in direct contact with the mirror layer; a conductive material layer disposed over and in direct contact with the second diffusion barrier layer; and a light emitting structure disposed over and in direct contact with the conductive material layer, wherein the light emitting structure includes a first semiconductor material, a second semiconductor material, and an active region disposed between the first semiconductor material and the second semiconductor material.
 18. The light emitting device of claim 17, further comprising at least one electrode disposed over the light emitting structure. 